Field of the Invention
The present invention relates to a method for the simulation of an error in a logic circuit which is designed for the optional connection of two logical levels to a circuit node via at least two input circuits which are provided with switch elements, wherein output bit patterns are derived from input bit patterns via a simulation model containing the error, the output bit patterns to be compared to reference bit patterns which are valid for an error-free case, and to circuit arrangements for implementing the method.